LXTALE from Intel Corporation. Find the PDF Datasheet, Specifications and Distributor Information. (This Datasheet also supports the LXT PHY.) Applications. Product Features LXTALE – Extended (° to 85 °C amb.) ▫ LXTALC. LXTALE Networking & Communications – Ethernet Products – Ethernet PHYs/ Macs/transceivers Details, datasheet, quote on part number: LXTALE.
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August 7, 11 LXTA 3. During a hardware reset, auto-negotiation and speed configuration settings are read in from pins refer to Table 9 on page 30 for pin settings and to Table 43 on page 74 for register bit definitions.
August 7, 85 LXTA 3. This bit is only valid when auto negotiate is enabled, and is equivalent to Register bit 1. If JTAG datasheey is not used, these lxt917ale do not need to be terminated. The following occurs in 5 V fiber transceiver applications as shown in Figure See Figure 34 on page 67 for jabber timing parameters. Table 41 presents a complete register listing.
The value of this pin can be overridden by Register bit If one to four dribble bits are received, the nibble is passed across the MII, padded with dafasheet if lxt97ale. Table 42 is a complete memory map of all registers and Tables 43 through 58 provide individual register definitions. If another event occurs before the stretch timer expires then the stretch timer is reset and the stretch time is extended. Added Table 26 information. Signals a receive error condition has occurred.
Collision status is the secondary LED driver. It includes a state machine, data register array, and instruction register. This signal is asynchronous and is inactive during fullduplex operation. August 7, 41 LXTA 3. This pin provides bias current for the internal circuitry. It is used only during auto-negotiation, and is applicable only datashee twisted-pair links. The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by as much as 3 dB over an ideal all-analog equalizer.
Refer to Table 21 on eatasheet 57 for clock timing requirements. Intel’s patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters.
If the link pulses stop, the data transmission is disabled. Must be tied to ground through a When the network link is forced to datssheet specific configuration, the LXTA immediately begins operating adtasheet network interface as commanded.
RO 0 This bit indicates the status of the auto-negotiation variable base page. Unless otherwise specified tolerance: These pins drive LED indicators.
Current characterized errata are available on request. This results in improved receiver noise and cross-talk performance. See Figure 27 for recommended logic translator interface circuitry. It then returns to supplying IDLE symbols to the line driver.
LXTALE Datasheet PDF – Intel
During 10 Mbps operation, Manchester-encoded data is exchanged. When an event such as receiving a packet occurs it is edge detected and it starts the stretch timer. Default values of Register bits 4. Four slew rate settings refer to Table 4 on page 18 allow the designer to match the output waveform to the magnetic characteristics.
The LED pins are sensitive to polarity and automatically pull up or pull down to configure for either open drain or open collector circuits 10 ratasheet Max current rating lx9t71ale required by the hardware configuration. When the stretch timer expires the edge detector is reset so that a long event causes another pulse to be generated from the edge detector which resets the stretch timer and causes the LED driver to remain asserted.
Test Loopback is enabled when 0. August 7, 83 LXTA 3. A2 63 CRS 1. Functional operation under these conditions is not implied. All weak pad pull-up and pull-down resistors are disabled. Interrupt logic is shown in Figure 6. Carrier sense is not generated when a packet is transmitted and in full-duplex mode.
The MDIO registers are not accessible. Electrical Parameters Table August 7, 57 LXTA 3. August 7, 43 LXTA 3.